Why this subject matters
Computer Organization and Architecture (COA) is the study of how a computer actually runs your program: how instructions are stored, how the processor fetches and executes them, how data moves between memory and the processor, and how fast all of this happens. Every line of Java, Python or C you write is eventually turned into simple machine instructions that a piece of hardware executes one step at a time. COA is the layer that explains that hardware.
You need this for two reasons. First, it appears directly in campus placement tests and in interviews for core and systems roles: written tests at many Indian service and product companies include CPU-time calculations, Amdahl's law, number conversions and pipeline questions. Second, it makes you a better software engineer. Once you know why a cache miss costs hundreds of cycles or why a branch the processor cannot predict is slow, performance advice stops being folklore and starts making sense.
This first lesson builds the foundation for the whole track. Interviewers typically probe:
- the difference between organization and architecture,
- Von Neumann versus Harvard designs and the "Von Neumann bottleneck",
- the steps of the instruction cycle,
- the CPU performance equation and numerical problems on it,
- Amdahl's law, and
- RISC versus CISC.
We will cover each one with worked examples you can reproduce on paper.
Organization versus architecture
These two words are often used together, but they mean different things.
Computer architecture is the set of attributes of a computer that a programmer (or compiler) can see and rely on. It is the contract between software and hardware. It answers questions such as: What instructions exist? How many registers are there? How big is a word? How are memory addresses formed? How are negative numbers represented? This contract is called the Instruction Set Architecture (ISA). x86-64, ARMv8 and RISC-V are examples of ISAs.
Computer organization is how that contract is implemented in hardware. It covers things the programmer normally cannot see directly: the clock frequency, whether the processor is pipelined, how many cache levels there are and how large they are, the width of internal buses, whether multiplication uses a dedicated circuit or repeated addition, and which signals the control unit generates.
A simple test: if changing something would force you to recompile or rewrite programs, it is architecture. If programs keep running unchanged, only faster or slower, it is organization.
| Question | Architecture or organization? |
|---|---|
| Does the CPU have a multiply instruction? | Architecture |
| Is multiply done by a fast array multiplier or a slow shift-add loop? | Organization |
| How many general-purpose registers can instructions name? | Architecture |
| How large is the L2 cache? | Organization |
| Is memory byte-addressable, and is it little-endian? | Architecture |
| Is the processor pipelined with 5 or 14 stages? | Organization |
A concrete example
Intel and AMD both build processors for the x86-64 architecture. A program compiled for x86-64 runs on both. Yet their chips differ enormously inside: different cache sizes, different pipeline depths, different branch predictors. Same architecture, different organizations. Likewise, the ARMv8 architecture is implemented by small, low-power cores in budget phones and by large, wide cores in laptops.
Interview tip
Give the one-line definition and then an example: "Architecture is what the programmer sees, like the instruction set and number of registers; organization is how it is built, like cache size or pipelining. Intel and AMD chips share the x86-64 architecture but have different organizations, which is why the same binary runs on both at different speeds."
The stored-program idea
Early machines were programmed by rewiring cables and setting switches. The breakthrough was the stored-program concept: keep the program's instructions in the same kind of memory as the data, as plain numbers. The processor then reads instructions from memory one after another and executes them. Changing the program becomes as easy as loading different numbers into memory.
This idea is usually associated with John von Neumann's 1945 report on the EDVAC design, which is why the resulting structure is called the Von Neumann architecture.
Von Neumann architecture
In a Von Neumann machine, there is one memory holding both instructions and data, and one path (bus) between the processor and that memory.
+-----------------------------+
| CPU |
| +---------+ +----------+ |
| | Control | | ALU + | |
| | Unit | | Registers| |
| +---------+ +----------+ |
+--------------+--------------+
|
single bus (address,
data, control)
|
+--------------+--------------+
| Memory: instructions AND |
| data in one address space |
+-----------------------------+
|
+----+----+
| I/O |
+---------+
Its key properties:
- Instructions and data share one address space. An address like
0x1000might hold an instruction or a number; memory itself does not know which. - Instructions are executed sequentially unless an instruction (such as a jump) changes the order.
- A single bus carries both instruction fetches and data reads/writes.
The Von Neumann bottleneck
Because there is one path to memory, the processor cannot fetch the next instruction and read a data operand at the same moment; they take turns. And processors became far faster than memory over the decades. The result is that the processor often sits idle waiting for memory. This limit on throughput, caused by the narrow channel between CPU and memory, is called the Von Neumann bottleneck.
Most of modern computer architecture, especially caches, prefetching and wide buses, can be read as an attempt to soften this bottleneck.
Harvard architecture
A Harvard machine uses separate memories (and separate buses) for instructions and for data.
+--------------+ +-------+ +--------------+
| Instruction |<------>| CPU |<------>| Data |
| memory | instr | | data | memory |
+--------------+ bus +-------+ bus +--------------+
Because the two paths are independent, the processor can fetch the next instruction while it reads or writes data for the current one. That doubles the available memory bandwidth for the same bus width.
Harvard machines are common in microcontrollers and digital signal processors (DSPs). For example, many small microcontrollers keep the program in on-chip flash and data in separate SRAM, with different address spaces for each.
Comparison
| Feature | Von Neumann | Harvard |
|---|---|---|
| Memory for code and data | One shared memory | Two separate memories |
| Buses | One shared bus | Separate instruction and data buses |
| Simultaneous instruction fetch and data access | No | Yes |
| Hardware cost | Lower | Higher (two memories and buses) |
| Flexibility | Memory split decided freely at run time | Split fixed by hardware |
| Self-modifying code, loading programs as data | Natural | Awkward |
| Typical use | General-purpose computers (conceptually) | Microcontrollers, DSPs |
Modified Harvard: what real CPUs do
Your laptop's processor is neither purely one nor the other. It is a modified Harvard design:
- Main memory (RAM) is a single unified memory holding both code and data, as in Von Neumann. Programs are loaded as data and then executed. The programmer sees one address space.
- Close to the core, the level-1 (L1) cache is split into an L1 instruction cache and an L1 data cache, each with its own path into the pipeline, as in Harvard. So the processor can fetch instructions and load data in the same cycle.
- Lower cache levels (L2, L3) are usually unified again.
+-----------------------------+
| Core |
| fetch load/ |
| unit store |
+----+------------------+-----+
| |
+-----+-----+ +-----+-----+
| L1 I-cache| | L1 D-cache| <- Harvard-style split
+-----+-----+ +-----+-----+
+--------+---------+
|
+------+------+
| L2 / L3 | <- unified
+------+------+
|
+------+------+
| Main memory| <- unified (Von Neumann)
+-------------+
This gets the bandwidth benefit of Harvard where it matters most (inside the core) while keeping the flexibility of one memory for software.
Common mistake
Saying "modern PCs are Von Neumann machines" is only half right. Programmers see a Von Neumann model (one address space), but the hardware uses split L1 instruction and data caches, which is a Harvard idea. The precise answer is "modified Harvard".
Main components of a computer
Every general-purpose computer has the same four building blocks.
1. The CPU (central processing unit)
The CPU executes instructions. Inside it:
- ALU (arithmetic logic unit): the circuit that does arithmetic (add, subtract) and logic (AND, OR, compare).
- Registers: a small number of very fast storage cells inside the CPU, each holding one word (for example 64 bits). Some are visible to programs (general-purpose registers); some are internal, such as the program counter (PC), which holds the address of the next instruction, and the instruction register (IR), which holds the instruction being executed.
- Control unit: reads each instruction and generates the signals that tell the ALU, registers and memory what to do in each step.
2. Memory
Memory stores programs and data. It forms a hierarchy: registers (fastest, tiny), caches (fast, small), main memory or RAM (slower, large), and secondary storage such as SSDs (slowest, largest, persistent). Each step down is larger and cheaper per byte but slower. Later lessons cover caches and virtual memory in detail.
3. Input/output (I/O)
I/O devices connect the computer to the outside world: keyboard, display, network card, disk. The CPU talks to them through device controllers, using techniques such as polling, interrupts and direct memory access (DMA). These are covered in the I/O organization lesson.
4. Buses (the interconnect)
A bus is a shared set of wires that carries information between components. A classic system bus has three parts:
| Bus | Carries | Direction | Width decides |
|---|---|---|---|
| Address bus | The memory or device address being accessed | CPU to memory/devices | How much memory can be addressed: n lines address 2^n locations |
| Data bus | The actual data being read or written | Both ways | How many bits move per transfer |
| Control bus | Signals such as read, write, clock, interrupt request, bus grant | Both ways | Which operations are possible |
Worked example. A CPU has a 32-bit address bus and memory is byte-addressable (every byte has its own address). How much memory can it address?
- Number of addresses =
2^32= 4,294,967,296. - Each address is one byte, so the limit is 4,294,967,296 bytes = 4 GiB.
This is exactly why 32-bit systems were limited to 4 GiB of address space per process, and why the move to 64-bit addresses mattered.
Modern machines replace one shared bus with point-to-point links (such as PCI Express lanes and on-chip interconnects), because a single shared bus cannot keep up with many fast components. The concept of address, data and control information remains the same.
The instruction cycle
The instruction cycle is the sequence of steps the CPU repeats for every instruction. The classic textbook version has three phases (fetch, decode, execute). The version used for pipelined RISC processors, and the one you should know, has five:
- Fetch (IF): read the instruction at the address in the PC from memory into the IR. Increment the PC to point at the next instruction.
- Decode (ID): work out what the instruction is (its opcode) and which registers it uses. Read those source registers.
- Execute (EX): the ALU does the work: adds, compares, or computes a memory address.
- Memory access (MEM): if the instruction is a load or store, read from or write to data memory. Other instructions skip this.
- Write-back (WB): write the result into the destination register.
After write-back, the CPU checks for pending interrupts (signals from devices or timers asking for attention). If one is pending and enabled, it saves its state and jumps to the interrupt handler; otherwise it starts the next fetch.
+-------+ +--------+ +---------+ +--------+ +-----------+
| Fetch |-->| Decode |-->| Execute |-->| Memory |-->| Write-back|
+-------+ +--------+ +---------+ +--------+ +-----+-----+
^ |
| interrupt pending? -- yes --> handler |
+------------------------- no ------------------------+
Tracing an example
Consider this short program for a simple RISC machine. Each instruction is 4 bytes. Registers are named x1, x2, and so on. Before it runs: x2 = 0x2000, memory at 0x2000 holds 10, memory at 0x2004 holds 32.
Address Instruction Meaning
0x100 lw x5, 0(x2) x5 = Mem[x2 + 0]
0x104 lw x6, 4(x2) x6 = Mem[x2 + 4]
0x108 add x7, x5, x6 x7 = x5 + x6
0x10C sw x7, 8(x2) Mem[x2 + 8] = x7
Let us trace the first instruction, lw x5, 0(x2), with PC = 0x100:
| Step | What happens | State after |
|---|---|---|
| Fetch | Read 4 bytes at address 0x100 into IR. PC = PC + 4. | IR = lw x5, 0(x2), PC = 0x104 |
| Decode | Opcode says "load word". Source register x2 is read. Immediate offset 0 is extracted. | Operands: 0x2000, offset 0 |
| Execute | ALU computes the address: 0x2000 + 0. | Address = 0x2000 |
| Memory | Read the word at 0x2000. | Value = 10 |
| Write-back | Write 10 into x5. | x5 = 10 |
The second load does the same with offset 4, giving x6 = 32 and PC = 0x108.
Now add x7, x5, x6:
| Step | What happens |
|---|---|
| Fetch | IR = add x7, x5, x6, PC = 0x10C |
| Decode | Read x5 = 10 and x6 = 32 |
| Execute | ALU adds: 10 + 32 = 42 |
| Memory | Nothing (not a load or store) |
| Write-back | x7 = 42 |
Finally sw x7, 8(x2):
| Step | What happens |
|---|---|
| Fetch | IR = sw x7, 8(x2), PC = 0x110 |
| Decode | Read x2 = 0x2000 and x7 = 42 |
| Execute | Address = 0x2000 + 8 = 0x2008 |
| Memory | Write 42 to address 0x2008 |
| Write-back | Nothing (a store produces no register result) |
Notice two things. Not every instruction needs every step. And steps like "fetch the next instruction" and "do arithmetic for this one" use different hardware, which is the opening that pipelining exploits: start fetching instruction 2 while instruction 1 is decoding. That is lesson 6.
Fetch-decode-execute vs five stages
Older textbooks describe a three-step "fetch, decode, execute" cycle, sometimes with "fetch operand" and "store result" as extra steps. These are the same ideas at different levels of detail. In an interview, state the five-stage version and mention that memory access and write-back are folded into "execute" in the three-step version.
Measuring performance
"Which computer is faster?" sounds simple, but you need precise definitions before you can answer it.
Response time and throughput
- Execution time (also called response time or latency): how long one task takes from start to finish.
- Throughput: how many tasks finish per unit time.
They are different. Adding more cores to a web server raises throughput (more requests per second) without making any single request faster. Replacing the processor with a faster one usually improves both.
We say "X is n times faster than Y" when
Performance(X) / Performance(Y) = ExecutionTime(Y) / ExecutionTime(X) = n
where performance is 1 / execution time.
Clock, cycles and CPI
A processor is driven by a clock, a signal that ticks at a fixed rate. Each tick starts a new clock cycle.
- Clock rate (frequency)
f: cycles per second, measured in hertz. 3 GHz = 3 × 10^9 cycles per second. - Clock cycle time
T: the length of one cycle,T = 1 / f. At 3 GHz,T= 0.333 ns. - Instruction count (IC): how many instructions the program executes (dynamically, counting each loop iteration).
- CPI (cycles per instruction): the average number of clock cycles each instruction takes.
The CPU performance equation
Putting these together:
CPU time = Instruction count x CPI x Clock cycle time
= (Instruction count x CPI) / Clock rate
Read it as units: instructions/program × cycles/instruction × seconds/cycle = seconds/program.
This equation is the most important formula in the subject, because it shows the three levers that change performance and who controls each:
| Factor | Influenced by |
|---|---|
| Instruction count | Algorithm, programming language, compiler, ISA |
| CPI | ISA, organization (pipelining, caches), compiler (instruction choice), program's memory behavior |
| Clock cycle time | Organization (pipeline depth), circuit technology |
Improving one factor often worsens another. A deeper pipeline raises the clock rate but may raise CPI through more stalls. A richer ISA may cut instruction count but lengthen the cycle. Only the product matters.
Worked example 1: basic CPU time
A program executes 2 × 10^9 instructions on a 3 GHz processor with an average CPI of 1.5. What is the CPU time?
- Total cycles = IC × CPI = 2 × 10^9 × 1.5 = 3 × 10^9 cycles.
- CPU time = cycles / clock rate = 3 × 10^9 / 3 × 10^9 = 1.0 second.
Worked example 2: CPI from an instruction mix
Different instruction classes take different numbers of cycles. The average CPI is a weighted average, using each class's fraction of executed instructions.
| Class | Fraction of instructions | Cycles each |
|---|---|---|
| ALU | 50% | 1 |
| Load | 20% | 3 |
| Store | 10% | 2 |
| Branch | 20% | 2 |
CPI = 0.50 x 1 + 0.20 x 3 + 0.10 x 2 + 0.20 x 2
= 0.50 + 0.60 + 0.20 + 0.40
= 1.70
If this program runs 10^9 instructions on a 2 GHz machine, CPU time = 10^9 × 1.7 / (2 × 10^9) = 0.85 seconds.
Which class should the designer speed up? Loads contribute 0.60 of the 1.70 cycles, the largest share, even though ALU instructions are more frequent. Always look at contribution (fraction × cycles), not just frequency.
Worked example 3: comparing two machines
Machine A runs at 2 GHz with CPI 2.0. Machine B runs at 3 GHz with CPI 3.5 for the same program (same ISA, so same instruction count I). Which is faster, and by how much?
- Time per instruction on A = CPI × T = 2.0 × (1 / 2 GHz) = 2.0 × 0.5 ns = 1.0 ns.
- Time per instruction on B = 3.5 × (1 / 3 GHz) = 3.5 × 0.333 ns = 1.167 ns.
- CPU time A =
I× 1.0 ns; CPU time B =I× 1.167 ns. - A is faster by 1.167 / 1.0 = about 1.17 times.
B has the higher clock rate but loses because its CPI is much worse. This is the "megahertz myth": clock rate alone does not tell you which machine is faster.
MIPS and MFLOPS, and why they mislead
MIPS (millions of instructions per second) is defined as:
MIPS = Instruction count / (Execution time x 10^6) = Clock rate / (CPI x 10^6)
MFLOPS (millions of floating-point operations per second) counts only floating-point operations.
Both look like natural speed measures, but they have serious pitfalls:
- They ignore what each instruction does. A CISC instruction may do the work of several RISC instructions. Comparing MIPS across different ISAs is meaningless.
- MIPS varies between programs on the same machine, because CPI depends on the instruction mix. There is no single MIPS rating for a computer.
- MIPS can move in the opposite direction from performance. A compiler that adds many cheap instructions can raise MIPS while making the program slower.
- MFLOPS depends on which operations count. A division may take much longer than an addition, but each counts as one operation; and operation sets differ between machines.
Worked example 4: higher MIPS, slower program
A 4 GHz machine has three instruction classes: A (CPI 1), B (CPI 2) and C (CPI 3). Two compilers produce code for the same program:
| Compiler | Class A (billions) | Class B (billions) | Class C (billions) |
|---|---|---|---|
| Compiler 1 | 5 | 1 | 1 |
| Compiler 2 | 10 | 1 | 1 |
Compiler 1:
- Cycles = 5 × 1 + 1 × 2 + 1 × 3 = 10 billion.
- Time = 10 × 10^9 / 4 × 10^9 = 2.5 s.
- Instructions = 7 billion. MIPS = 7 × 10^9 / (2.5 × 10^6) = 2,800.
Compiler 2:
- Cycles = 10 × 1 + 1 × 2 + 1 × 3 = 15 billion.
- Time = 15 × 10^9 / 4 × 10^9 = 3.75 s.
- Instructions = 12 billion. MIPS = 12 × 10^9 / (3.75 × 10^6) = 3,200.
Compiler 2's code has the higher MIPS rating (3,200 vs 2,800) but takes 50% longer (3.75 s vs 2.5 s). It just executes more cheap instructions. The only reliable measure is execution time of real programs, which is why benchmark suites such as SPEC CPU report times (or ratios of times), not MIPS.
Common mistake
Never compare processors by clock rate or MIPS alone. Use the full equation: time = IC × CPI × cycle time. Numerical questions are often designed so that the machine with the higher clock rate or higher MIPS turns out to be slower.
Speedup
Speedup compares an old and a new system on the same work:
Speedup = Execution time (old) / Execution time (new)
A speedup of 2 means the new system takes half the time.
Amdahl's law
You make part of a program faster. How much faster does the whole program get? Amdahl's law answers this. It is named after Gene Amdahl, who presented the argument in 1967.
Let:
f= the fraction of the original execution time that benefits from the improvement,s= the speedup of that fraction alone.
The unimproved part, 1 - f, takes the same time as before. The improved part now takes f / s. So:
1
Overall speedup = -----------------
(1 - f) + f / s
As s grows without limit, f / s goes to 0, and the speedup approaches 1 / (1 - f). The part you do not improve sets a hard ceiling.
Worked example 5: speeding up 80% of a program
80% of a program's time is spent in a loop. You make the loop 4 times faster.
f = 0.8,s = 4.- New time (as a fraction of old) = (1 - 0.8) + 0.8 / 4 = 0.2 + 0.2 = 0.4.
- Overall speedup = 1 / 0.4 = 2.5.
The loop got 4 times faster, but the whole program only 2.5 times. Even an infinitely fast loop would give at most 1 / 0.2 = 5 times.
Worked example 6: what speedup do you need?
Same program (f = 0.8). You want the whole program to be 4 times faster. How fast must the loop become?
- Set 1 / (0.2 + 0.8 / s) = 4.
- So 0.2 + 0.8 / s = 0.25.
- So 0.8 / s = 0.05, giving s = 16.
The loop must become 16 times faster to get a 4 times overall speedup. And an overall speedup of 5 or more is impossible no matter what you do to the loop.
Worked example 7: parallel processors
A program is 90% parallelizable. What is the speedup on 10 cores? On an unlimited number?
- 10 cores: 1 / (0.1 + 0.9 / 10) = 1 / (0.1 + 0.09) = 1 / 0.19 ≈ 5.26.
- Unlimited: 1 / 0.1 = 10.
Ten cores give barely more than half of ideal. This is why serial bottlenecks (locks, single-threaded setup, I/O) dominate parallel performance.
Interview tip
State the formula, then the takeaway: "Make the common case fast, but the part you don't speed up limits you to 1 over the serial fraction." If asked about parallel computing, mention Gustafson's law as the counterpoint: when the problem size grows with the number of processors, the parallel part grows too, so scaled speedup can keep rising.
RISC versus CISC
An ISA can be designed in two broad styles.
CISC (Complex Instruction Set Computer) designs offer many instructions, some of which do a lot of work, such as an instruction that reads two memory operands, adds them and writes the result to memory. Instructions have variable length and many addressing modes. The idea, from the era of expensive memory and assembly programming, was to make each instruction powerful so programs are short. x86 is the classic CISC ISA.
RISC (Reduced Instruction Set Computer) designs offer a smaller set of simple, regular instructions, typically each doing one simple thing in about one cycle when pipelined. Only load and store instructions access memory; arithmetic works on registers. Instructions have a fixed length (often 32 bits) and a few simple formats, which makes decoding and pipelining easy. ARM, RISC-V and MIPS are RISC ISAs.
| Aspect | RISC | CISC |
|---|---|---|
| Number of instructions | Fewer, simpler | Many, some complex |
| Instruction length | Fixed (for example 32 bits) | Variable (x86: 1 to 15 bytes) |
| Memory access | Only load/store (load-store architecture) | Many instructions can use memory operands |
| Addressing modes | Few | Many |
| Registers | Many general-purpose (often 32) | Historically fewer (x86-64 has 16 integer registers) |
| CPI | Close to 1 with pipelining | Varies widely per instruction |
| Instruction count | Higher | Lower |
| Control unit | Usually hardwired | Traditionally microprogrammed |
| Decoding | Simple | Complex |
| Pipelining | Easy | Harder; needs translation to simpler operations |
| Code density | Lower (larger programs) | Higher (smaller programs) |
| Burden | More on the compiler | More on the hardware |
In terms of the performance equation, CISC tries to cut instruction count; RISC accepts more instructions in exchange for lower CPI and a shorter cycle.
The modern reality: convergence
The line has blurred:
- Modern x86 processors decode complex x86 instructions into simpler internal micro-operations (µops) and execute those on a RISC-like pipelined core. So the inside looks RISC while the ISA stays CISC for compatibility.
- RISC ISAs have added complex features: ARM has compressed instructions (Thumb) for code density and vector extensions; RISC-V has an optional compressed (16-bit) extension.
The honest summary is that the ISA style matters less than it did in the 1980s; the organization (caches, branch prediction, out-of-order execution) dominates performance, while the ISA affects decoding complexity and power. RISC designs remain popular where energy efficiency and simple decoding matter, such as phones and embedded devices, and increasingly in laptops and servers.
Moore's law and the end of Dennard scaling
Two observations shaped processor design for decades.
Moore's law is Gordon Moore's observation (1965, revised in 1975) that the number of transistors on a chip doubles roughly every two years. It is an economic and engineering trend, not a law of physics. It held remarkably well for decades, though the pace has slowed as transistors approach atomic dimensions and each new manufacturing process becomes far more expensive.
Dennard scaling (from a 1974 paper by Robert Dennard and colleagues) observed that as transistors shrink, their voltage and current shrink too, so power per unit area stays roughly constant. In practice this meant each generation gave you more transistors that also switched faster, at about the same power density. Clock rates climbed rapidly through the 1990s and early 2000s.
Dennard scaling broke down around the mid-2000s. Voltages could no longer drop much further (transistors leak current when the voltage is too low relative to their switching threshold), so shrinking transistors and raising clock rates started increasing power density. Chips hit a power wall: they could not be cooled if clock rates kept climbing. Desktop clock rates have stayed within a few gigahertz since then.
The industry's response shaped everything you see today:
- Multicore processors: use the extra transistors for more cores at moderate clock rates, instead of one faster core. Software must now be parallel to benefit, which is where Amdahl's law bites.
- Specialization: dedicated hardware for graphics (GPUs), machine learning, video encoding and cryptography, because specialized circuits do more work per watt.
- Dark silicon: not all of a chip's transistors can be powered at full speed at the same time within the power budget.
- Energy efficiency became a first-class design goal alongside speed.
Power in one formula
Dynamic power of a chip is roughly proportional to capacitive load × voltage² × frequency. Because voltage is squared, lowering voltage was the main lever for saving power. When voltage stopped falling, raising frequency directly raised power, which is the power wall.
Interview questions
Q1. What is the difference between computer architecture and computer organization?
Architecture is the programmer-visible contract: the instruction set, register count, data types, addressing modes and memory model. Organization is how that contract is implemented: clock rate, pipelining, cache sizes, bus widths and control signals. Changing architecture breaks binary compatibility; changing organization does not. Intel and AMD x86-64 chips share an architecture but differ in organization.
Q2. What is the Von Neumann bottleneck and how is it reduced?
In a Von Neumann machine, instructions and data share one memory and one bus, so the CPU can do only one memory transfer at a time and spends much of its time waiting for slow memory. It is reduced with caches (especially split instruction and data L1 caches), wider buses, prefetching, and more memory channels. Out-of-order execution also helps by doing useful work while a memory access is pending.
Q3. Is a modern laptop CPU Von Neumann or Harvard?
It is a modified Harvard design. Main memory is unified and software sees a single address space, as in Von Neumann. But the L1 cache is split into instruction and data caches with separate paths, as in Harvard, so instruction fetch and data access can happen in the same cycle.
Q4. Walk through the instruction cycle for a load instruction.
Fetch reads the instruction at the PC into the IR and increments the PC. Decode identifies the opcode and reads the base register. Execute adds the base register and offset to form the address. Memory reads the word at that address. Write-back stores the value into the destination register. The CPU then checks for interrupts before the next fetch.
Q5. State the CPU performance equation and what affects each term.
CPU time = instruction count × CPI × clock cycle time. Instruction count depends on the algorithm, compiler and ISA. CPI depends on the ISA, the organization (pipelining, caches, branch prediction) and the program's behavior. Cycle time depends on organization and circuit technology. They interact, so only the product is a fair measure.
Q6. Why is a higher clock rate not always faster?
Execution time also depends on CPI and instruction count. A 3 GHz machine with CPI 3.5 takes 1.17 ns per instruction, while a 2 GHz machine with CPI 2.0 takes 1.0 ns, so the slower-clocked machine wins on the same program. Deep pipelines that raise the clock often raise CPI through stalls and misprediction penalties.
Q7. What is wrong with MIPS as a performance metric?
MIPS ignores how much work each instruction does, so it cannot compare different ISAs. It changes from program to program on the same machine. And it can rise while performance falls: a compiler that emits more cheap instructions can raise MIPS but increase run time. Execution time on representative benchmarks is the reliable measure.
Q8. State Amdahl's law. If 60% of a program is sped up by 3 times, what is the overall speedup?
Speedup = 1 / ((1 - f) + f / s). With f = 0.6 and s = 3: 1 / (0.4 + 0.2) = 1 / 0.6 ≈ 1.67. The maximum possible speedup from improving that 60% is 1 / 0.4 = 2.5.
Q9. What does Amdahl's law imply for multicore processors?
The serial fraction of a program limits the speedup regardless of core count. With 5% serial code, the maximum speedup is 20 even with thousands of cores. This is why reducing serial sections, contention and synchronization matters as much as adding cores. Gustafson's law gives a more optimistic view when problem size grows with the machine.
Q10. Compare RISC and CISC.
RISC uses a small set of simple, fixed-length instructions, a load-store design and many registers, aiming for CPI near 1 and easy pipelining at the cost of more instructions. CISC uses many variable-length instructions that can operate on memory directly, aiming for fewer instructions and denser code at the cost of complex decoding. Modern x86 chips translate CISC instructions into RISC-like micro-operations internally, so the difference today is mostly at the decode stage.
Q11. What are the address, data and control buses?
The address bus carries the location being accessed and its width sets the addressable memory (n lines give 2^n addresses). The data bus carries the values transferred, and its width sets how many bits move at once. The control bus carries signals such as read, write, clock and interrupt requests that coordinate the transfer.
Q12. What is Moore's law and is it still valid?
It is the observation that transistor counts per chip double about every two years. Transistor counts still increase, but more slowly and at much higher cost per new process. More importantly, Dennard scaling ended in the mid-2000s, so extra transistors no longer bring free clock-rate increases, which is why the industry shifted to multicore and specialized hardware.
Q13. Why did clock rates stop increasing around 2005?
Power density. Dynamic power grows with voltage squared times frequency. Once voltage could no longer be lowered with each new process because of leakage, higher frequency meant more heat than chips could dissipate. Designers used the transistor budget for more cores, bigger caches and accelerators instead.
Q14. What is the difference between response time and throughput?
Response time is how long one task takes; throughput is how many tasks complete per unit time. Adding processors or servers usually improves throughput without reducing the time for one task, while a faster processor improves both. Pipelining is a classic example of improving throughput while each instruction's latency stays the same or even grows slightly.
Key takeaways
- Architecture is the programmer-visible contract (the ISA); organization is the hardware implementation of it.
- Von Neumann uses one memory and one bus for code and data, creating the Von Neumann bottleneck; Harvard separates them. Real CPUs are modified Harvard: unified main memory with split L1 caches.
- A computer consists of the CPU (ALU, registers, control unit), memory hierarchy, I/O, and the interconnect (address, data and control buses).
- The five-stage instruction cycle is fetch, decode, execute, memory access and write-back, followed by an interrupt check.
- CPU time = instruction count × CPI × clock cycle time. Compute average CPI as a weighted sum over the instruction mix.
- Clock rate and MIPS alone are misleading; only execution time on real programs is reliable.
- Amdahl's law: speedup = 1 / ((1 - f) + f / s); the unimproved fraction caps the gain at 1 / (1 - f).
- RISC trades more instructions for low CPI and simple pipelines; CISC trades complex decoding for fewer instructions. Modern x86 is RISC-like inside.
- The end of Dennard scaling created the power wall and drove the shift to multicore and specialized accelerators.
Next lesson
Continue with Data representation.